A prior art computer or data processing system typically includes a central processing unit ("CPU") that is coupled to a storage system. The CPU can be implemented by a microprocessor. The storage system typically includes a number of memory devices. Each of the memory devices can be accessed by the CPU.
In order to select a memory device from a number of memory devices for a memory operation, the CPU needs to generate a chip select signal to the selected memory device. The chip select signal then activates or enables the selected memory device to receive addresses and control information from the CPU for the desired read or write operation. Currently, there are a number of prior art schemes for selecting a memory device from a number of memory devices.
FIG. 1 shows one prior art scheme of selecting a memory device from a number of memory devices. As shown in FIG. 1, each of memory chips or devices 13a through 13f is connected to a CPU 11 via bus 12. In addition, each of memory devices 13a-13f includes a chip enable input CE that receives one of a number of chip select signals CS0 through CS5 from CPU 11 via one of a number of chip select lines 14a through 14f coupled between CPU 11 and memory devices 13a-13f. For example, memory device 14a receives the chip select signal CS0 via line 14a and memory device 13d receives the chip select signal CS3 via line 14d. When, for example, CPU 11 needs to access memory device 13b, CPU 11 asserts the CS1 chip select signal via line 14b to memory device 13b. This causes memory device 13b to be enabled to receive address and other information from CPU 11 via bus 12 for the desired read or write operation.
Disadvantages are, however, associated with the above-described prior art scheme. One disadvantage is that CPU 11 needs to be individually connected to each of the chip select lines 14a-14f in order to individually asserts each of the chip select signals CS0 through CS5. This typically causes the CPU to have a relatively large number of chip select pins. When the number of memory devices increases, the number of CPU pins used to supply the chip select signals increases accordingly. As is known, a pin typically requires relatively large die area to construct. Therefore, a CPU with a large number of pins is typically large in size.
One prior art solution to this problem is shown in FIG. 2. As can be seen from FIG. 2, memory devices 23a through 23i are arranged in an array 23. In addition, a chip select signal decoder 22 is connected between CPU 21 and array 23. Decoder 22 decodes a chip select data from CPU 21 to assert one of the column select signals CS.sub.Y0 through CS.sub.Y2 and one of the row select signals CS.sub.X0 through CS.sub.X2 . The memory device at the intersection of the asserted row and column select signals is the selected memory device. FIG. 3 shows in block diagram form the circuitry of each of memory devices 23a through 23i.
As can be seen from FIGS. 2 and 3, the number of memory devices 23a-23i is greater than the total number of the column and row chip select signals CS.sub.Y0 -CS.sub.Y2 and CS.sub.X0 -CS.sub.X2 . In addition, the number of pins required for CPU 21 to supply the chip select data is also less than the total number of the column and row chip select signals CS.sub.Y0 -CS.sub.Y2 and CS.sub.X0 -CS.sub.X2 generated by decoder 22. This therefore allows CPU 21 and decoder 22 to have fewer pins for providing the chip select signals. As can be seen from FIG. 2, only six chip select signals (i.e., CS.sub.Y0 -CS.sub.Y2 and CS.sub.X0 -CS.sub.X2 ) are used to select nine memory devices 23a-23i. Also, CPU 21 only needs to supply a four-bit chip select data to generate these chip select signals.
As the integrated circuit fabrication and packaging technologies advance, a memory device package can contain more than one memory chip or device. FIGS. 4 through 6 illustrate one prior art scheme of selecting a memory device from an array of memory packages 33a through 33i, wherein each of memory packages 33a-33i includes two memory devices (shown in FIG. 5). As can be seen from FIG. 4, memory packages 33a-33i are still arranged in an array 33. Each of memory packages 33a-33i receives two of the row select signals CS.sub.X0 through CS.sub.X5 . Again, as can be seen from FIGS. 4-6, decoder 32 uses fewer select signals to select among a relatively large number of memory chips arranged in an array.
The above-described prior art scheme still bears disadvantages. One disadvantage is that if each of memory packages 33a-33i includes only one memory device, the array configuration shown in FIG. 4 is no longer suitable and therefore needs to be changed. However, it is typically difficult to change the array configuration because, as is known, the array configuration is typically part of a printed circuit board ("PCB") layout. To change the array configuration simply means using a separate printed circuit board.